1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, the present invention relates to a trench-capacitor dynamic random access memory (DRAM) with a folded gate conductor and method of fabrication thereof.
2. Description of the Prior Art
A memory chip is an integrated circuit (IC) made of millions of transistors and capacitors. In the most common form of computer memory, dynamic random access memory (DRAM), a MOS transistor and a storage capacitor are paired to create a memory cell, which represents a single bit of data. Memory cells are etched onto a silicon wafer in an array of columns (bitlines) and rows (wordlines). The intersection of a bitline and wordline constitutes the address of the memory cell. The storage capacitor holds the bit of information. The MOS transistor acts as a switch that lets the control circuitry on the memory chip read the storage capacitor or change its state. The storage capacitor typically comprises a top electrode, a storage node, and a capacitor dielectric layer.
DRAM devices having deep trench (DT) capacitors are well known in the art. In the case of DRAM, in order to fabricate a lot of memory cells in the same memory device, the base area of the memory cells must be small. At the same time, the electrode plates of the capacitors of the memory cells must have sufficient surface area to store enough charge. Because cell size determines chip density, size and cost, reducing cell area is the DRAM designer's primary goal. Cell area may be reduced by shrinking the individual feature size, or by forming structures, which make more efficient use of the chip surface area. The latter approach is particularly desirable. In a typical process for fabricating trench-capacitor DRAMs, the capacitor structure is completely formed prior to the formation of the transistor gate conductor (GC) structure. Thus, a typical process sequence involves the steps of opening the trench, filling the trench, forming the node conductors, then forming the gate stack structure.